Sub-5 nm Gate-Length Monolayer Selenene Transistors

Two-dimensional (2D) semiconductors are being considered as alternative channel materials as silicon-based field-effect transistors (FETs) have reached their scaling limits. Recently, air-stable 2D selenium nanosheet FETs with a gate length of 5 µm were experimentally produced. In this study, we used an ab initio quantum transport approach to simulate sub-5 nm gate-length double-gate monolayer (ML) selenene FETs. When considering negative-capacitance technology and underlap, we found that 3 nm gate-length p-type ML selenene FETs can meet the 2013 ITRS standards for high-performance applications along the armchair and zigzag directions in the 2028 horizon. Therefore, ML selenene has the potential to be a channel material that can scale Moore’s law down to a gate length of 3 nm.


Introduction
The short channel effect of silicon field-effect transistors (FETs) exceeds the physical limits of FETs, making them difficult to apply [1][2][3]. Therefore, the search for a new material to replace silicon is crucial. When successfully foliated, two-dimensional (2D) semiconductors have begun competing with graphene as a future channel material [4,5]. The newly created 2D Xenes (silicene, phosphorene, tellurene, and so on) have the potential to surpass the limitations in practical applications because of their uniform thickness, higher electrostatic gate control, simple elemental composition, and other properties [6,7]. The on/off-state current ratio of sub-10 nm gate length (L g ) monolayer and bilayer tellurene FETs with p-type characteristics is 10 8 and 10 6 , respectively [8,9]. The p-type monolayer (ML) tellurene transistor meets the criterion for the International Technology Roadmap for Semiconductors (ITRS), with a gate length of 4 nm [9]. Thus, investigating 2D monoelemental semiconductors, which have good carrier mobility and air stability for use in logic circuits, is required [6,7,[9][10][11][12][13][14][15][16].
Selenium, which is known for its essential role in biological systems, has received attention in the realm of physical sciences [17][18][19][20][21][22]. The thermal properties of 2D α-selenene were investigated by Liu et al., revealing its remarkable thermophysical characteristics. At a temperature of 300 K, 2D α-selenene exhibited an excellent thermal conductivity of 3.04 W/(m·K). The study by Liu et al. further emphasized the crucial role played by relaxation time in controlling the thermal transport behavior of 2D α-selenene [23]. Lin et al. conducted a detailed investigation into the thermoelectric properties of 2D ML square selenene, using a comprehensive approach to reveal a significant anisotropy in the thermal performance of the material. These findings provided valuable insights into the complex relationship between directionality and the thermal transport behavior of ML square selinene [22].
The photonic properties of 2D selenium nanosheets have also been investigated, revealing remarkable findings regarding the photoresponsivity and temporal characteristics of selenium nanosheet phototransistors. The photoresponsivity measurement has achieved an impressive value of 263 A/W, accompanied by the rapid rise and fall times of 0.1 s and 0.12 s, respectively [17]. These results indicate that ML square selenene is a potential material for thermoelectric and photonic devices in the future.
Back-gated FETs were fabricated by employing p-type selenium nanosheets with 5 µm L g , using the physical vapor-deposition technique. The resulting FETs demonstrated a low on-state current (I on ) of approximately 20 A/m at V dd = 3 V, which can be attributed to the presence of zigzag edges in the selenium nanosheets. Selenene, a 2D form of selenium, is fabricated in such a way that it is atomically thin [17]. Nevertheless, there is currently a knowledge gap in the existing literature about the fabrication and characterization of sub-5 nm L g selenene FETs .
This study presents a theoretical evaluation of the performances of sub-5 FETs using ab inito quantum transport simulations. The ITRS high-performance (HP) criteria were met by the I on of the 3 nm L g p-type selenene FETs (p-type 3 FETs) with underlap (UL) along the armchair direction (arm-direction) and the I on of the 1 nm L g p-type selenene FETs (p-type 1 FETs) with UL were approximately 17.55% and 1.90%, respectively, for the ITRS HP criteria along the armchair and zigzag directions (the arm-direction and the zigdirection). After considering the negative-capacitance (NC) effect and UL, the p-type 3 FETs met the ITRS HP criteria along both the arm-direction and the zig-direction. These results demonstrate that ML selenene is a potential channel material that is capable of extending Moore's law by 3 nm.

Device Structure
The optimal lattice parameters of ML selenene are a = 3.76 Å, c = 6.52 Å, based on previous theoretical work [19,20]. Lattice structures of ML selenene from both top and side views are presented in Figure 1a. Figure 1b depicts the band structure of ML selenene using a double-zeta polarized (DZP) basis set in QuantumATK, showing an indirect band gap of 1.0 eV and exceeding the expected theoretical value of 0.73 eV (DFT/PBE) by a small amount, which is close to the theoretical value of 1.13 eV (DFT/HSE06) [24,25]. Figure 1c presents the n-and p-doped ML selenene, serving as channels and electrodes for the sub-5-FETs. A UL area was the uncovered part of the channel by the gate electrode, which was added between the source/drain electrode and gate. UL is an effective method to extend the effective channel length [26][27][28]. We executed the test for doping concentration to provide the best possible device performance ( Figure S1). According to the test for doping concentration, we found that the off-state current of the 5 nm gate length n-type selenene FETs can not meet I off for ITRS HP along the armchair direction, except for doping concentration n = 5 × 10 12 cm −2 , as shown in Figure S1. Thus, the on-state current of the 5 nm gate length p-type selenene FETs is higher than that of n-type selenene FETs. The slope of transfer characteristics curves of the 5 nm gate length p-type selenene FETs is larger than that of n-type selenene FETs. Therefore, the p-type ML selenene FETs perform better than the n-type ones in the device. As a result, we exclusively investigated p-type ML selenene FETs in the arm-and zig-directions, and we adopted the doping concertation to 5 × 10 13 cm −2 in the following calculations.

On-State Current
A critical figure of merit for the logic transistor is the I on . Figure 2 depicts the transfer characteristic curve of the sub-5 FETs along the arm-and zig-directions. According to ITRS 2013, V dd is the power supply voltage, chosen as V dd = 0.64 V, I off = 0.1 µA/µm. We can obtain the off-state voltage (V g,off ) from transfer characteristics curves of the sub-5 nm gate lengths selenene FETs at the off-state current (I off ). Thus, the on-state voltage and current (V g,on and I on ) can be obtained. Figure 2 can determine V g,on = V g,off ±V dd ("+" and "−" Molecules 2023, 28, 5390 3 of 11 sign corresponds to n-and p-types) [29]. The power supply voltage is denoted by V dd , according to ITRS 2013, V dd = 0.64 V, I off = 0.1 µA/µm. The transfer current is calculated using the width normalization, and the width is 3.761 Å (6.515 Å) along the arm-(zig-) direction throughout the whole paper. All the p-type sub-5 FETs without UL cannot comply with the ITRS HP requirement along the arm-and zig-directions. After summarizing I on in various L g and UL lengths listed in Tables 1 and 2, suitable UL lengths could significantly improve I on for both the arm-and zig-directions in the ITRS HP application. The I on of the p-type 3 FETs with L UL = 3 nm was 1010.32 µA/µm along the armchair directions, whereas the I on (571.02 µA/µm) of the p-type 3 FETs with L UL = 2 nm was 63% of the ITRS for HP goal along the zig-directions, as shown in Figure 3.

On-State Current
A critical figure of merit for the logic transistor is the Ion. Figure 2 depicts the transfer characteristic curve of the sub-5 FETs along the arm-and zig-directions. According to ITRS 2013, Vdd is the power supply voltage, chosen as Vdd = 0.64 V, Ioff = 0.1 µA/µm. We can obtain the off-state voltage (Vg,off) from transfer characteristics curves of the sub-5 nm gate lengths selenene FETs at the off-state current (Ioff). Thus, the on-state voltage and current (Vg,on and Ion) can be obtained. Figure 2 can determine Vg,on = Vg,off ±Vdd ("+" and "−" sign corresponds to n-and p-types) [29]. The power supply voltage is denoted by Vdd, according to ITRS 2013, Vdd = 0.64 V, Ioff = 0.1 µA/µm. The transfer current is calculated using the width normalization, and the width is 3.761 Å (6.515 Å) along the arm-(zig-) direction throughout the whole paper. All the p-type sub-5 FETs without UL cannot comply with the ITRS HP requirement along the arm-and zig-directions. After summarizing Ion in various Lg and UL lengths listed in Tables 1 and 2, suitable UL lengths could significantly improve Ion for both the arm-and zig-directions in the ITRS HP application. The Ion of the p-type 3 FETs with LUL = 3 nm was 1010.32 µA/µm along the armchair directions, whereas the Ion (571.02 µA/µm) of the p-type 3 FETs with LUL = 2 nm was 63% of the ITRS for HP goal along the zig-directions, as shown in Figure 3.           Figure 4 presents spectrum characteristics of the 5 nm L g p-type selenene FETs (ptype 5 FETs) with L UL = 1 nm in the HP application, allowing us to observe gate modulation along the arm-direction. Examples will be shown to demonstrate the spectrum current and position-resolved local density of states (LDOS) at on-, intermediate-, and off-states. The distance between the source's Fermi level and the channel's lowest valence band maximum is known as the hole activation energy (Φ B ). As V g rises from 0.08 to 0.72 V, the channel's band edge tilts downwards, increasing from 0 to 0.34 eV. Consequently, the total current (I total ) in the device comprises tunnel and thermal current (I tunnel and I therm ). Figure S2 depicts the 5 FETs with L UL = 1 nm in the zig-direction. The gate modulation mechanism of the p-type 5 FETs with L UL = 1 nm in the zig-direction is similar to that in the arm-direction.    Figure 4 presents spectrum characteristics of the 5 nm Lg p-type selenene FETs (ptype 5 FETs) with LUL = 1 nm in the HP application, allowing us to observe gate modulation along the arm-direction. Examples will be shown to demonstrate the spectrum current and position-resolved local density of states (LDOS) at on-, intermediate-, and offstates. The distance between the source's Fermi level and the channel's lowest valence band maximum is known as the hole activation energy (ΦB). As Vg rises from 0.08 to 0.72 V, the channel's band edge tilts downwards, increasing from 0 to 0.34 eV. Consequently, the total current (Itotal) in the device comprises tunnel and thermal current (Itunnel and Itherm).    Figure 4 presents spectrum characteristics of the 5 nm Lg p-type selenene FETs (ptype 5 FETs) with LUL = 1 nm in the HP application, allowing us to observe gate modulation along the arm-direction. Examples will be shown to demonstrate the spectrum current and position-resolved local density of states (LDOS) at on-, intermediate-, and offstates. The distance between the source's Fermi level and the channel's lowest valence band maximum is known as the hole activation energy (ΦB). As Vg rises from 0.08 to 0.72 V, the channel's band edge tilts downwards, increasing from 0 to 0.34 eV. Consequently, the total current (Itotal) in the device comprises tunnel and thermal current (Itunnel and Itherm). Figure

Gate Controlling Ability
The subthreshold swing (SS = ∂Vg/∂(logIds)) is crucial in determining the ability of ML selenene FET to gate control [9,14]. We can obtain the SS from transfer characteristics curves of the sub-5 nm gate lengths selenene FETs in the subthreshold zone. A smaller SS offers higher gate control capability in the subthreshold zone. Figure 5 illustrates how the UL structure promotes SS growth as the Lg decreases in the p-type 5 FETs. Along the armdirection, the SS of the p-type 5/3/1 FETs with UL structure is 100.39/117.19/178.68 mV/decade, respectively. The SS of the p-type sub-5 FETs with UL structure along the zigdirection is similar to that of the device in the arm-direction.

Gate Controlling Ability
The subthreshold swing (SS = ∂V g /∂(logI ds )) is crucial in determining the ability of ML selenene FET to gate control [9,14]. We can obtain the SS from transfer characteristics curves of the sub-5 nm gate lengths selenene FETs in the subthreshold zone. A smaller SS offers higher gate control capability in the subthreshold zone. Figure 5 illustrates how the UL structure promotes SS growth as the L g decreases in the p-type 5 FETs. Along the arm-direction, the SS of the p-type 5/3/1 FETs with UL structure is 100. 39 respectively. The SS of the p-type sub-5 FETs with UL structure along the zig-direction is similar to that of the device in the arm-direction.
The subthreshold swing (SS = ∂Vg/∂(logIds)) is crucial in determining the ability of ML selenene FET to gate control [9,14]. We can obtain the SS from transfer characteristics curves of the sub-5 nm gate lengths selenene FETs in the subthreshold zone. A smaller SS offers higher gate control capability in the subthreshold zone. Figure 5 illustrates how the UL structure promotes SS growth as the Lg decreases in the p-type 5 FETs. Along the armdirection, the SS of the p-type 5/3/1 FETs with UL structure is 100.39/117.19/178.68 mV/decade, respectively. The SS of the p-type sub-5 FETs with UL structure along the zigdirection is similar to that of the device in the arm-direction.

τ, PDP and EDP
The switching speed of ML selenene FETs is determined by the effective delay time (τ = CtVdd/Ion). Ct = Cg + Cf, Cg(f) is the gate (fringing) capacitance, and Cg = ∂Qch/∂Vg. According to ITRS 2013, Cg is equal to half of Cf. The QuantumATK 2019 software package was used with the DZP basis set to derive the total Mulliken charge (Qch) in the central region [24]. Furthermore, the Ct values of the p-type sub-5 FETs are smaller than the ITRS HP goal along the arm-direction. However, the Ct (0.2 fF/µm) of the p-type 3 FETs with LUL = 3 nm is smaller than the ITRS HP along the zig-direction, as shown in Figure S3. The Ct of p-type 3 FETs along the arm-direction is lower than that of the ones along the zigdirection for the same Lg. The response speed of the p-type 3 FETs in the arm-direction is faster than the device along the zig-direction, because of combining small Ct and large Ion to create a high-speed switch.

τ, PDP and EDP
The switching speed of ML selenene FETs is determined by the effective delay time (τ = C t V dd /I on ). C t = C g + C f , C g(f) is the gate (fringing) capacitance, and C g = ∂Q ch /∂V g . According to ITRS 2013, C g is equal to half of C f . The QuantumATK 2019 software package was used with the DZP basis set to derive the total Mulliken charge (Q ch ) in the central region [24]. Furthermore, the C t values of the p-type sub-5 FETs are smaller than the ITRS HP goal along the arm-direction. However, the C t (0.2 fF/µm) of the p-type 3 FETs with L UL = 3 nm is smaller than the ITRS HP along the zig-direction, as shown in Figure S3. The C t of p-type 3 FETs along the arm-direction is lower than that of the ones along the zig-direction for the same L g . The response speed of the p-type 3 FETs in the arm-direction is faster than the device along the zig-direction, because of combining small C t and large I on to create a high-speed switch.
The switching energy of ML selenene FETs is measured using power dissipation (PDP = V dd I on τ). Figure S4 shows that the PDP values of the p-type sub-5 FETs decrease with increasing L g along both the arm-and zig-directions. Along the arm-direction, all PDPs of the p-type ML selenene FETs with UL can meet the ITRS HP criteria.
In Figure 6, we also include the energy-delay product (EDP) of p-type sub-5 FETs. EDP can be defined as EDP = PDP × τ, taking into account both response speed and energy dissipation. The minimum EDP value specified by ITRS requirements, as well as the EDP values for p-type sub-5 FETs and ML Teurene (Te) FETs reports, are plotted in red, pink, and blue lines, respectively. Except for the p-type 3 and 1 FETs with UL along a zig-direction, all of the p-type sub-5 FETs have EDP values that are lower than the EDP of ITRS HP criteria for the 2028 horizon (1.02 × 10 −28 J·s/µm). The p-type ML selenene FETs have the lowest EDP value at 1.5 × 10 −29 J·s/µm when L g is set to 3 nm. It can be compared with those of ML MoS 2 [30], InSe [31], Bi 2 O 2 Se [32], and Tellurene FETs [9]. The EDP of p-type ML selenene FETs is higher than that of ML InSe, Bi 2 O 2 Se, and tellurene FETs. It is roughly 17 times greater than the minimum EDP (9.02 × 10 −31 J·s/µm) for ML tellurene FETs, but only slightly higher than the minimum EDP (1.34 × 10 −30 J·s/µm) for ML MoS 2 FETs. tion, all of the p-type sub-5 FETs have EDP values that are lower than the EDP of ITRS HP criteria for the 2028 horizon (1.02 × 10 −28 J·s/μm). The p-type ML selenene FETs have the lowest EDP value at 1.5 × 10 −29 J·s/μm when Lg is set to 3 nm. It can be compared with those of ML MoS2 [30], InSe [31], Bi2O2Se [32], and Tellurene FETs [9]. The EDP of p-type ML selenene FETs is higher than that of ML InSe, Bi2O2Se, and tellurene FETs. It is roughly 17 times greater than the minimum EDP (9.02 × 10 −31 J·s/μm) for ML tellurene FETs, but only slightly higher than the minimum EDP (1. 34 Figure 6. PDP versus τ of ML MoS2 [30], InSe [31], Bi2O2Se [32], and Tellurene FETs (along the armand zig-direction) [9] for the HP applications, respectively. Solid lines are the minimum ITRS requirements for the energy-delay product EDP = τ × PDP. Dot and dash dot lines are the minimum EDP value of the p-type sub-5 FETs and ML tellurene FETs reports, respectively.

Discussion
Many 2D transistors are suitable for HP applications, such as ML MoS2 [30], ML InSe [31], ML and bilayer (BL) Bi2O2Se [32,33], ML and BL tellurene [8,9], and ML silicane [15], and so on. Several transport simulations of 2D semiconductors transistors based on the DFT + NEGF method are used to explore the potential channel candidates for post-silicon nanoelectronics. ML MoS2 and ML silicane can extend Moore's law to 5 nm, respectively. ML InSe can extend Moore's law to 3 nm. ML and BL Bi2O2Se can extend Moore's law to 2 and 5 nm, respectively. ML and BL tellurene can extend Moore's law to 4 and 9 nm, respectively.
The Ion is a critical figure of merit for the logic transistor, to figure out the key factor that affects Ion, the relationship between the effective mass (m*) and Ion of the suggested model at various 5 nm Lg 2D semiconductors FETs is displayed in Figure 7 [30], InSe [31], Bi 2 O 2 Se [32], and Tellurene FETs (along the arm-and zig-direction) [9] for the HP applications, respectively. Solid lines are the minimum ITRS requirements for the energy-delay product EDP = τ × PDP. Dot and dash dot lines are the minimum EDP value of the p-type sub-5 FETs and ML tellurene FETs reports, respectively.

Discussion
Many 2D transistors are suitable for HP applications, such as ML MoS 2 [30], ML InSe [31], ML and bilayer (BL) Bi 2 O 2 Se [32,33], ML and BL tellurene [8,9], and ML silicane [15], and so on. Several transport simulations of 2D semiconductors transistors based on the DFT + NEGF method are used to explore the potential channel candidates for post-silicon nanoelectronics. ML MoS 2 and ML silicane can extend Moore's law to 5 nm, respectively. ML InSe can extend Moore's law to 3 nm. ML and BL Bi 2 O 2 Se can extend Moore's law to 2 and 5 nm, respectively. ML and BL tellurene can extend Moore's law to 4 and 9 nm, respectively.
The I on is a critical figure of merit for the logic transistor, to figure out the key factor that affects I on , the relationship between the effective mass (m*) and I on of the suggested model at various 5 nm L g 2D semiconductors FETs is displayed in Figure 7 [9,[30][31][32]. When m* < 0.68 m 0 , I on decreases with increasing m*, and I on is at its lowest when m* ≈ 0.68 m 0 . For m* > 0.68 m 0 , I on increases with increasing m*. Tiny m* results in a higher I on and greater carrier velocities (v = eEτ/m*), which are determined by the e (charge), E (electric field), and τ, respectively. The current can be written as I = nev, where n is the carrier concentration. The density of states (DOS) of the transport channel is negligibly tiny. DOS is written as is the spin (valley) degeneracies, is the reduced Plank constant, and m * x(y) is the transverse (transport) effective mass. Larger m* leads to slower velocity, but the DOS of the transport channel is enough; thus, I on is high. According to Figure 7, the competition between m* and DOS results in a dominant factor affecting I on . The anisotropy has been found in many 2D materials, such as ML BP [34,35], 2D BiAs [36], ML and BL tellurene [8,9], and ML selinene [19], and so on. The physical properties (elastic modulus, effective mass, deformation potential, and carrier mobility) of ML selenene are different between the arm-and zig-direction. Using the software package QuantumATK 2019, the effective mass (m*) of ML selenene was obtained from the band structure; the hole effective mass of ML selenene is 0.14 m 0 and 0.43 m 0 along the armand zig-direction, respectively. It is consistent with previous reports in the literature [19]. The hole effective mass of ML selenene along the arm-direction is lighter than that of the zig-direction, and the I on (1717.80 µA/µm) of p-type 5 FETs along the arm-direction is larger than that (1269.00 µA/µm) of the device along the zig-direction, as shown in Table S1. The I on of ML selenene are different between arm-and zig-direction with 3 nm and 1 nm gate length. Along the arm-direction, the m* (0.14 m 0 ) of the hole for ML selenene is lighter than that (0.39 m 0 ) of the ML tellurene, the I on (1717.81 µA/µm) of ML selenene is larger than that (951 µA/µm) of ML tellurene. Along the zig-direction, the effective mass (0.43 m 0 ) of ML selenene is larger than that (0.11 m 0 ) of ML tellurene, so the I on (1269 µA/µm) of ML selenene is smaller than that (2114 µA/µm) of ML tellurene.
along the arm-and zig-direction, respectively. It is consistent with previous reports in the literature [19]. The hole effective mass of ML selenene along the arm-direction is lighter than that of the zig-direction, and the Ion (1717.80 µA/µm) of p-type 5 FETs along the arm-direction is larger than that (1269.00 µA/µm) of the device along the zig-direction, as shown in Table S1. The Ion of ML selenene are different between arm-and zig-direction with 3 nm and 1 nm gate length. Along the arm-direction, the m* (0.14 m0) of the hole for ML selenene is lighter than that (0.39 m0) of the ML tellurene, the Ion (1717.81 µA/µm) of ML selenene is larger than that (951 µA/µm) of ML tellurene. Along the zig-direction, the effective mass (0.43 m0) of ML selenene is larger than that (0.11 m0) of ML tellurene, so the Ion (1269 µA/µm) of ML selenene is smaller than that (2114 µA/µm) of ML tellurene. We added a negative-capacitance (NC) gate stack to the ferroelectric materials to further enhance the performances of the p-type sub-5 FETs in Figure S5a [9,37]. We found that the Ion of the device increased, and the SS of p-type sub-5 FETs with the same Lg and UL decreased, but the Ion of the device increased. It is already known that the NC voltage is VNC = −3.822 × 10 8 × tFEQ + 2.3529 × 10 10 tFEQ 3 of Hf0.5Zr0.5O2 ferroelectric material [38,39]. The electrical charge is represented by the symbol Q. The thickness of the ferroelectric layer is denoted by tFE, and for the ML selenene FETs, we incorporated a ferroelectric layer that was 50 nm thick.
Tables S2 and S3 compare the Ion and SS with those without NC for p-type sub-5 FETs with and without NC at LUL = 2 nm. Figure S5b compares the arm-and zig-direction transfer properties of p-type sub-5 FETs at Lg = 5 nm. Generally, the SS of p-type sub-5 FETs with NC is lower than those of p-type sub-5 FETs without NC. The minimum value of SS (81.26 mV/dec) is obtained by p-type 5 FETs with NC and LUL = 2 nm along the arm-direction. The Ion of p-type sub-5 nm FETs with NC is greater than those of p-type sub-5 FETs without NC. All Ion of p-type 5 FETs and 3 FETs with NC and UL satisfy the 2028 requirements (900 µA/µm) of ITRS HP application along arm-and zig-direction, respectively. The maximum value of Ion  We added a negative-capacitance (NC) gate stack to the ferroelectric materials to further enhance the performances of the p-type sub-5 FETs in Figure S5a [9,37]. We found that the I on of the device increased, and the SS of p-type sub-5 FETs with the same L g and UL decreased, but the I on of the device increased. It is already known that the NC voltage is V NC = −3.822 × 10 8 × t FE Q + 2.3529 × 10 10 t FE Q 3 of Hf 0.5 Zr 0.5 O 2 ferroelectric material [38,39]. The electrical charge is represented by the symbol Q. The thickness of the ferroelectric layer is denoted by t FE , and for the ML selenene FETs, we incorporated a ferroelectric layer that was 50 nm thick.
Tables S2 and S3 compare the I on and SS with those without NC for p-type sub-5 FETs with and without NC at L UL = 2 nm. Figure S5b compares the arm-and zig-direction transfer properties of p-type sub-5 FETs at L g = 5 nm. Generally, the SS of p-type sub-5 FETs with NC is lower than those of p-type sub-5 FETs without NC. The minimum value of SS (81.26 mV/dec) is obtained by p-type 5 FETs with NC and L UL = 2 nm along the arm-direction. The I on of p-type sub-5 nm FETs with NC is greater than those of p-type sub-5 FETs without NC. All I on of p-type 5 FETs and 3 FETs with NC and UL satisfy the 2028 requirements (900 µA/µm) of ITRS HP application along arm-and zig-direction, respectively. The maximum value of I on (3202.95 µA/µm) is obtained by p-type 5 FETs with NC and L UL = 2 nm along the arm-direction. In contrast, the maximum value of I on is 3.55 times greater than the ITRS criteria for HP application.

Model and Approach
Using the software package QuantumATK Version P-2019.03, which combines the density functional theory (DFT) and the nonequilibrium Green's function (NEGF), the transport characteristics of sub-5 FETs can be determined [24,26,40,41]. The following Landauer-Bűttiker formula is used to determine the drain current at a given bias (gate) voltage V b(G) [41]: where e and h are the elementary charges and the Planck constant, respectively, and the electrochemical potential and the Fermi-Dirac distribution function for the source (drain) Molecules 2023, 28, 5390 9 of 11 are denoted by µ S(D) and f S(D) , respectively. The transmission coefficient is denoted by T(E, V b , V G ). FHI pseudopotential is used with the basis set of polarized double zeta. The exchange-correlation interaction is described using the generalized gradient approximation (GGA) as the Perdew-Burke-Ernzerhof (PBE) function [26,[42][43][44]. The DFT method, which is based on GGA with single-electron approximation, is useful in characterizing a device's electronic structure. This method is effective in modeling the electronic behavior of a device by doping the carriers with a strongly screened electron-electron interaction [45]. The k-point meshes in the Brillouin zone are set to Monkhorst-Pack 7 × 1 × 145 for the electrode and the central region. The temperature and real-space mesh cutoff are 300 K and 30 Ha, respectively. The boundary conditions for the x, y, and z axes are Neumann, Periodic, and Dirichlet, respectively. The z-axis is always the path of transport.

Conclusions
In the current work, the performance of the sub-5 FETs was first examined. With the proper UL structure, the I on , τ, and PDP of the p-type 3 (5) FETs satisfy the ITRS HP criteria along the arm-(zig-)directions. After considering the NC effect and UL, the p-type 3 FETs can meet ITRS HP criteria along both arm-and zig-directions. Therefore, ML selenene has the potential to be used as a channel material for HP devices and extend Moore's Law down to the 3 nm scale.
Supplementary Materials: The following supporting information can be downloaded at: https:// www.mdpi.com/article/10.3390/molecules28145390/s1. Figure S1: Transfer characteristics of the nand p-type 5 FETs with varying doping concentrations along arm-and zig-directions; Figure S2: LDOS and spectrum current of the p-type 5 FETs with L UL = 1 nm at the on-, intermediate-and off-state; Figures S3 and S4: the τ and PDP vs. L g in the p-type sub-5 FETs with different UL along the armand zig-directions; Figure S5: A schematic presentation of the ML selenene FETs with the ferroelectric layers; Transfer characteristics of the p-type 5 FETs at L UL = 2 nm with and without NC dielectric; Tables S1-S3: Summary of I on and SS values of the p-type sub-5 FETs for the HP application between with and without NC dielectric along the arm-and zig-direction.
Author Contributions: Q.L. is an expert in 2D materials and transistors. He was involved in performing the conceptualization, software, methodology, writing, and funding acquisition. X.T. is an expert in 2D materials and transistors. He was involved in performing the conceptualization, software, methodology, writing, and validation. Y.Y. is an expert in 2D materials and transistors. He was involved in performing the conceptualization, methodology, writing, and validation. X.X. is an expert in 2D materials and 2D materials transistors. He was involved in performing the software, formal analysis, writing, and validation. T.Z. is an expert in 2D materials. He was involved in performing the formal analysis, writing, validation, and funding acquisition. Z.W. is an expert in 2D materials. He was involved in performing the software, formal analysis, writing, and validation. All authors have read and agreed to the published version of the manuscript.